隨著集成電路器件尺寸的不斷微縮，全包圍環形柵（Gate-all-around）器件成為先進工藝節點的重要技術，然而GAA器件工藝復雜，技術挑戰巨大。

       As the size of IC devices continues to shrink, gate-all-around devices have become an important technology for advanced process nodes. However, the technical challenges are still huge in terms of the process fabrication.

     上海集成電路材料研究院聯合中科院上海微系統所研發具有內嵌空腔的SOI襯底（Void Embedded Silicon on Insulator，即VESOI）（圖1），并成功應用于GAA器件的制備。

      The Shanghai Institute of IC Materials (SICM) and the Shanghai Institute of Microsystem and Information Technology Chinese, Academy of Sciences (SIMIT, CAS) developed an SOI substrate (Void Embedded Silicon-on-Insulator, VESOI) with embedded cavities (Figure 1), and successfully applied it in the fabrication of GAA devices.

圖1 SOI與VESOI襯底對比  Figure 1 SOI substrate vs. VESOI

      研發團隊制備出8英寸VESOI襯底（圖2），實現了空腔結構在SOI襯底中的高密度排列。在8英寸VESOI襯底上，利用與普通平面CMOS工藝完全兼容的工藝流程，制備出GAA器件（圖3）。

       The research team developed an 8-inch VESOI substrate (Figure 2), which achieved the high-density arrangement of the cavity structure in the SOI substrate. GAA devices are fabricated on an 8-inch VESOI substrate using a process flow that is fully compatible with common planar CMOS processes (Figure 3).

圖2 8英寸VESOI襯底實物圖  Figure 2 8-inch VESOI substrate

圖3 GAA器件流程簡要示意圖  Figure 3 Schematic diagram of GAA device process flow

      VESOI GAA器件的柵極完全包裹了導電溝道，溝道上方和下方的柵氧層厚度一致，并表現出了優異的電學性能（圖4），其最小亞閾值斜率小于63mV/dec，電流密度較平面SOI器件最高可提升150%以上。

       The gate of the VESOI GAA device completely wraps the conductive channel with the same gate oxide thickness above and below the channel. And the device shows excellent electrical performance (Figure 4). Its minimum subthreshold slope is less than 63mV/dec, and the current density can be increased by more than 150% compared with planar SOI devices.

圖4 基于VESOI襯底的GAA器件表現出優良電學性能  Figure 4 Excellent electrical performance on GAA devices based on VESOI substrate

      與目前常用的GAA器件工藝相比，VESOI GAA器件工藝大大簡化，并可兼容大部分工藝節點。VESOI GAA既可用于先進工藝節點器件，也可對成熟工藝節點進行性能升級。研發團隊同時還在開發將VESOI應用于傳感器、射頻器件等一系列技術，以期滿足更廣泛的應用需求。

      Compared with the commonly-used GAA device process recently, the VESOI GAA device fabrication is significantly simplified and compatible with most planar process nodes. It can be used not only in processes beyond advanced nodes, but also for upgrading performance on mature ones.The research team is developing a series of technologies that apply VESOI to sensors, RF devices, etc., to meet a wider range of application requirements.

    上海集成電路材料研究院  Shanghai Institute of IC Materials

    上海集成電路材料研究院由中國科學院上海微系統與信息技術研究所和上海硅產業集團股份有限公司發起組建，聚焦集成電路襯底材料、工藝材料和前沿技術的研發與產業化。

     The Shanghai Institute of IC Materials was initiated and established by the SIMIT, CAS and National Silicon Industry Group, focusing on the R&D and industrialization of integrated circuit substrate materials, fabrication materials and cutting-edge technologies.

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